1. Field of the Invention
The present invention generally relates to the field of circuit design. More specifically, the present invention relates to a microprocessor clock signal distribution architecture.
2. Background Information
In recent years, numerous advancements in the field of microprocessor design and fabrication have enabled microprocessor clock frequencies to be continuously increased. Unfortunately however, as clock frequencies tend to increase, the absolute skew and jitter that can be tolerated by systems tends to decrease in proportion to the inverse of the clock frequency. Accordingly, the effort and expense required to meet the low skew and jitter design requirements have continued to increase along with the clock frequencies, thereby hindering and even delaying the development of faster processor chips.
FIG. 1 illustrates a simplified schematic of an H-tree clock distribution network in accordance with the prior art. As shown, H-tree clock network 100 includes clock source 102, clock receivers 104, and transmission lines 106 to distribute clock signals from clock source 102 to each clock receiver 104, which generally represents a buffer that drives a local clock distribution grid. Conventional microprocessor clock signals are typically distributed using such H-trees where each of the signal transmission lines are designed to be equal in length to avoid introduction of clock skew. Perhaps the most challenging aspect of global microprocessor clock design involves maintaining thousands of clock distribution points at the same electrical length in the presence of obstacles such as signal lines. More specifically, the balancing of the electrical lengths of thousands of branches of an H-tree, particularly in the presence of obstacles, is a major source of design complexity that is increasingly exposing designs to simulation inaccuracies and tapeout delays. However, despite the significant industry-wide work that has been invested to overcome this problem, a simplified clock distribution solution that operates within present-day power, area and design time constraints has not yet been found.